The present invention relates to delay lines, i.e. to integrated circuits which can impose a delay in the transmission of a digital pulse.
Delay lines are often used by system designers to adjust the timing of various events in electronic systems. For example, they may be used to adjust sampling times in high-speed analog systems, or to avoid possible collisions in asynchronous digital systems.
Delay lines commonly provide a capacitor, a source of charging current for the capacitor, a reset switch (to discharges the capacitor), and a thresholding stage. An incoming pulse (whenever one arrives) causes the reset switch to be opened, so that the capacitor begins to charge. The capacitor is charged up until voltage is high enough to activate the thresholding stage. The output of the thresholding stage provides a digital signal which is propagated through to the output. After the reset switch closes (discharging the capacitor), the delay line is ready for a new cycle.
In this general architecture, the resulting delay will be affected by the capacitor size, by the size of the charging current, and by the trigger voltage of the thresholding gate. If one or more of these factors can be varied, the delay will be adjustable. This is most commonly done by changing the magnitude of the charging current (or sometimes by changing the other parameters listed). The capability to "program" in the delay time is very useful to system designers.
The charging current is usually taken from a current source (having a fixed maximum current I.sub.charge), so the dependence of the delay is very simple: it is approximately equal to (C.sub.int V.sub.trip)/T.sub.charge, where V.sub.trip is the trigger voltage of the thresholding stage and C.sub.int is the value of the capacitor. (Alternatively, if the charging current is limited by a resistor, the charging current will decrease as the voltage on the capacitor increases, so the delays will be slightly less simple to calculate.)
The present invention provides a novel integrated circuit delay line, which includes several features of novelty. These features are particularly advantageous for a high-speed delay lines, e.g. where delays as short as 10 nsec or less may be needed.
In the presently preferred embodiment, the integration capacitor is implemented using a capacitance of relatively small value. (In fact, in the preferred embodiment, this capacitor is implemented using a parasitic capacitance, of which the largest component is the parasitic drain-to-substrate capacitance of the reset transistor.) The use of a small capacitor value has two principal advantages: the delay line can operate at very short delays, and dynamic power consumption is reduced (for a given delay time).
To optimize the characteristics of this parasitic capacitor, the reset transistor is preferably laid out as a circle (more precisely, with a circular lateral boundary between the drain and the channel). This permits the parasitic drain capacitance (which is used as the integration capacitor for timing) to be minimized for a given channel width (or for a given transconductance). Thus, in the mask layout of FIG. 6, it can be seen that the drain is an island which is surrounded by a circular channel. The channel surrounds the drain, and the source region surrounds the channel. (The drain and source regions are shallow n+ diffusions, which are self-aligned to the overlying polysilicon layer.) Diode capacitors have a capacitance/voltage relation which is inherently somewhat nonlinear, but this layout helps to minimize the nonlinearities. (Such nonlinearities tend to be undesirable in a delay line, since they mean that variations in the supply voltage may cause variations in the delay time.)
Another innovative feature disclosed herein is the use of a two-part structure, which partially resembles a DAC (digital-to-analog converter), to define equivalent resistance at a pull-down node. This resistance has a very simple relation to the resulting net delay, and this simple relation provides simple control. (By contrast, if current is used as the controlled variable, the resulting inverse relation will not be as simple to calculate, and therefore will not be as susceptible to control by low-level hardware.)
This structure has several additional advantages. The problem of providing a precisely controlled current is thus decomposed into separate problems of voltage control and resistance control. Both of these problems have been addressed separately, and improvements in both of these areas are continuing to occur. Many circuits have been developed to adjust a reference voltage for temperature variation. By performing such modifications to the reference voltage (instead of using a feedback arrangement to monitor the current), such compensation is simpler. By using a simple resistor circuit for voltage-to-current conversion, current level selection can easily be performed in the resistor structure, with high repeatability. Moreover, existing DAC circuit architectures (or improved DAC architectures which may be introduced in the future) can easily be adapted for use in a programmable delay line (or other circuit) according to the present invention.
In the presently preferred embodiment, temperature compensation is performed in two stages: first, a reference voltage V.sub.REF is made to be as nearly temperature-independent as possible (consistent with mass production of an integrated circuit which has a low power budget). In addition, a compensation signal V.sub.COMP provides a control signal to the delay line stages, which they can use to compensate for temperature dependence within the delay stage.
A further feature is the use of high-resistivity polysilicon features which have a negative temperature coefficient of resistance. This helps to provide improved temperature compensation, by helping to center the compensation component of the reference voltage. The parallel variation of resistance and voltage helps to maintain a constant current over a broad temperature range.
Another feature is that the delay line is configured using two identical halves. The output of the two halves is combined to produce an exactly symmetrical waveform. This is particularly advantageous in a programmable delay line, since this architecture assures that control changes which change the delay will not change the pulse width of the output waveform.
A further innovative teaching is provided by the alternative embodiment shown in FIG. 7. In this embodiment, the delay cell uses an innovative self-timed precharge cycle. While the capacitor is charging, a parallel (and faster) circuit path brings the output of the thresholding circuit to a predetermined precharge level. This increases the noise margin of the output, and helps to accommodate a wide range of possible delay times.